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Stéphane BURIGNAT

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    Author / Editor / Organization Title Year Journal / Proceedings / Book BibTeX type DOI/URL
    De Vos, A., Burignat, S. & Thomsen, M. Reversible implementation of a discrete integer linear transformation

    [Abstract] [BibTeX]

    		 2012 Journal of Multiple-Valued Logic and Soft Computing
    Vol. 18(1), pp. 25-35     		 article   URL
    Abstract: Discrete linear transformations form important steps in processing information. Many such transformations are injective and therefore are prime candidates for a physically reversible implementation into hardware. We present here the first steps towards a reversible digital implementation of two different integer transformations on four inputs: The Haar wavelet and the H.264 transform.
    BibTeX: 
    @article{2012_JMVLSC_De_Vos,
  author = {De Vos, A. and Burignat, S. and Thomsen, M.K.},
  title = {Reversible implementation of a discrete integer linear transformation},
  journal = {Journal of Multiple-Valued Logic and Soft Computing},
  year = {2012},
  volume = {18},
  number = {1},
  pages = {25--35}
}
    Burignat, S., Olczak, M., Klimczak, M. & De Vos, A. Towards the Limits of Cascaded Reversible (Quantum-Inspired) Circuits

    [Abstract] [BibTeX]

    		 2011 to be published in Lecture Notes in Computer Science article   Soon on LNCS
    Abstract: Several prototypes and proofs of concept of reversible (quantum-inspired) digital circuits have been successfully realized these last years, proving that digital reversible dual-line pass-transistor technology may be used for reversible linear computations. In order for this new technology to be used in commercial applications, several questions have to be answerd first. In particular, the number of gates possibly cascaded, the maximum reachable frequency, the maximum acceptable delays and amplitude drops are the key issues discussed in this paper.
    BibTeX: 
    @article{2011_LNCS_Burignat_Cascade,
  author = {Burignat, S. and Olczak, M and Klimczak, M and De Vos, A.},
  title = {Towards the Limits of Cascaded Reversible (Quantum-Inspired) Circuits},
  journal = {to be published in Lecture Notes in Computer Science},
  year = {2011}
}
    Burignat, S., Thomsen, M., Klimczak, M., Olczak, M. & De Vos, A. Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits

    [Abstract] [BibTeX]

    		 2011 to be published in Lecture Notes in Computer Science article   Soon on LNCS
    Abstract: Important progress has been made recently in the prototyping of reversible (quantum) digital circuits, proving that digital reversible dual-line pass-transistor technology may be used for applications in reversible linear computation. This raises new questions regarding the compatibility of this new technology with existing standard switching CMOS technology. The greatest difficulty is brought by the difference of signal shape used by the two technologies. Whereas standard switching CMOS circuits make use of rectangular pulses, dual-line pass-transistor reversible circuits use adiabatic triangular or trapezoidal ones. This work proposes a simple technical solution that allows interfacing digital reversible pass-transistor with conventional CMOS switching technology represented here by a Xilinx FPGA embedded on a commercial Spartan-3E board. All the proposed solutions have successfully been tested, allowing the FPGA to practically drive a reversible chip.
    BibTeX: 
    @article{2011_LNCS_Burignat_Interface,
  author = {Burignat, S. and Thomsen, M.K. and Klimczak, M and Olczak, M and De Vos, A.},
  title = {Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits},
  journal = {to be published in Lecture Notes in Computer Science},
  year = {2011}
}
    Burignat, S. & De Vos, A. Test of a Majority-based Reversible (Quantum) 4 bits Ripple-carry Adder in Adiabatic Calculation

    [Abstract] [BibTeX]

    		 2011 Proceedings of the 18th International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES~2011), pp. 368-373  inproceedings   Soon in IEEEXplore
    Abstract: Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of circuits dedicated to quantum computation. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. As a proof of concept we designed and tested a reversible 4 bits ripple-carry adder based on a do-spy-undo structure. This paper presents some performances obtained with such a chip processed in standard 0.35 μm CMOS technology and used in real reversible calculation (in this study, computations are performed in both directions such that addition and subtraction are made reversibly with the same chip). We also discuss the superiority of using adiabatic signals over classical rectangular pulses when using dual-line pass-transistor logic gates. Adiabatic signals allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat. Finally, we show that adiabatic signals allow to avoid calculation errors introduced by the use of conventional rectangular pulses and allow to drastically reduce the number of pulse resynchronization in large circuits.
    BibTeX: 
    @inproceedings{2011_MIXDES_Burignat,
  author = {Burignat, S. and De Vos, A.},
  title = {Test of a Majority-based Reversible (Quantum) 4 bits Ripple-carry Adder in Adiabatic Calculation},
  booktitle = {Proceedings of the 18$^th$ International Conference "Mixed Design of Integrated Circuits and Systems" (MIXDES~2011)},
  year = {2011},
  pages = {368--373}
}
    Burignat, S. Conduction par pièges dans les films minces de dioxyde de silicium

    [Abstract] [BibTeX]

    		2010 Éditions Universitaires Européennes, 268 pages,
    ISBN-13: 978-6131513800       		book   URL 
    Abstract: Le marché des mémoires non volatiles à grille flottante connaît un essor considérable du fait de leur utilisation croissante dans tous les domaines d'applications de la microélectronique et par conséquent dans de très nombreux secteurs industriels.

    Cependant, ces dispositifs mémoires se heurtent à une limite technologique liée à l'impossibilité de réduire l'épaisseur de la couche d'oxyde tunnel isolant la grille flottante contenant l'information, sans atteindre le domaine des courants de fuite induits (Stress Induced Leakage Current). Ces fuites engendrent des pertes de charge qui diminuent drastiquement le temps de rétention et la durée de vie des cellules mémoires.

    à travers ce livre riche en détails techniques et scientifiques, l'auteur aborde successivement les nombreuses étapes indispensables qui doivent être prises en compte lors du développement d'outils de caractérisation adaptés à la mesure des courants SILC inférieurs à fA.

    Il explique également, en les justifiant, chaque étape de la construction d'un modèle de conduction assisté par des pièges situés dans l'oxyde de grille et permettant de réaliser l'extraction des profils spatial et énergétique de ces défauts.
    BibTeX: 
    @book{2010_EUE_Burignat,
  author = {Burignat, Stéphane},
  title = {Conduction par pièges dans les films minces de dioxyde de silicium},
  publisher = {Éditions Universitaires Européennes},
  year = {2010},
  pages = {268},
  url = {http://www.google.be/search?&q=9786131513800+OR+6131513805}
}
    Burignat, S.; Flandre, D.; Arshad, M.M.; Kilchytska, V.; Andrieu, F.; Faynot, O. & Raskin, J.-P. Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

    [Abstract] [BibTeX]

    		2010 Solid-State Electronics
    Vol.54, pp.213-219     		article DOI   URL 
    Abstract: This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage (Vthf) and subthreshold slope (S), for sub-32 nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145 nm (UTB) or thin 11.5 nm (UTB2). This study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1 [mu]m down to 25 nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact on the electrical parameters Vthf and S. Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling.
    BibTeX: 
    @article{2010_SSE_Burignat,
      author = {S. Burignat and D. Flandre and M.K. Md Arshad and V. Kilchytska and F. Andrieu and O. Faynot and J.-P. Raskin},

      title = {Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel},
      journal = {Solid-State Electronics},
      year = {2010},
      volume = {54},
      pages = {213-219},
      url = {http://www.sciencedirect.com/science/article/B6TY5-4Y0C2H1-4/2/ca10fa3d545d25d7d61a8c125087b90b},
      doi = {http://dx.doi.org/10.1016/j.sse.2009.12.021}
    }
    Rudenko, T.; Kilchytska, V.; Burignat, S.; Raskin, J.-P.; Andrieu, F.; Faynot, O.; Tiec, Y.L.; Landry, K.; Nazarov, A.; Lysenko, V. & Flandre, D. Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

    [Abstract] [BibTeX]

    		2010 Solid-State Electronics
    Vol.54, pp.164-170.     		article DOI   URL 
    Abstract: This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction channel in the film from front to back interface, and on the comparison between the two BOX thicknesses. It is found that the back-channel mobility significantly exceeds the front-channel mobility, which is presumably related to strongly different Coulomb scattering at the two interfaces, being in agreement with previously published experimental studies. Furthermore, the back-channel mobility is found to be the same for thick and thin BOX. This strongly suggests that BOX thinning does not degrade the quality of the back interface. The observed effect of much higher back-channel mobility, which is retained for the thin BOX, could find application for the additional improvement of the device performance, when adjusting the threshold voltage via back-gate bias. Adequate mobility interpretation is then required as a varying combination of front and back-channel mobilities.
    BibTeX: 
    @article{2010_SSE_Rudenko,
      author = {T. Rudenko and V. Kilchytska and S. Burignat and J.-P. Raskin and F. Andrieu and O. Faynot and Y. Le Tiec and K. Landry and A. Nazarov and V.S. Lysenko and D. Flandre},
      title = {Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides},
      journal = {Solid-State Electronics},
      year = {2010},
      volume = {54},
      pages = {164–170},
      url = {http://www.sciencedirect.com/science/article/B6TY5-4Y0K9TC-4/2/66749a9a8dfc2cae62573e50fe475029},
      doi = {http://dx.doi.org/10.1016/j.sse.2009.12.014}
    }
    Kranti, A.; Rashmi, R.; Burignat, S.; Raskin, J. & Armstrong, G. Analog/RF Performance of sub-100nm SOI MOSFETs with Non-Classical Gate-Source/Drain Underlap Channel Design

    [Abstract] [BibTeX]

    		2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2010) inproceedings   URL 
    Abstract: In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB)SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT)along with a broader analog `sweet spot' in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (~10 µA/µm)but extend up to 100 µA/µm which corresponds to optimum AVO and fT performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.
    BibTeX: 
    @inproceedings{2010_IEEE_SiRF_Kranti,
      author = {A. Kranti and R. Rashmi and S. Burignat and J. Raskin and G. Armstrong},
      title = {Analog/RF Performance of sub-100nm SOI MOSFETs with Non-Classical Gate-Source/Drain Underlap Channel Design},
      booktitle = {Proc. of the 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems 11-13 January 2010, New Orleans, LA},
      year = {2010},
      url = {http://www.silicon-rf.org/sirf2010/myFiles/General/SiRF_2010_Advance_Program.pdf}
     }
    Burignat, S.; Arshad, M.K.M.; Raskin, J.-P.; Kilchytska, V.; Flandre, D.; Faynot, O.; Scheiblin, P. & Andrieu, F. Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with undoped channel

    [Abstract] [BibTeX]

    		2009 Proc. European Solid State Device Research Conference (ESSDERC '09) , pp. 141-144   inproceedings DOI    
    Abstract: For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this drastically changes the channel position in the film and the drain coupling with the channel via substrate and through the BOX. Several modifications to the MASTAR DIBL model are proposed based on ATLAS simulations of the studied structures, in order to explain those effects and fit the experimental data.
    BibTeX: 
    @inproceedings{2009_IEEE_ESSDERC_Burignat,
  author = {Burignat, S. and Arshad, M. K. M. and Raskin, J.-P. and Kilchytska, V. and Flandre, D. and Faynot, O. and Scheiblin, P. and Andrieu, F. },
  title = {Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with undoped channel},
  booktitle = {Proc. European Solid State Device Research Conference ESSDERC '09},
  year = {2009},
  pages = {141--144},
  doi = {http://dx.doi.org/10.1109/ESSDERC.2009.5331323}
}
    Burignat, S.; Flandre, D.; Kilchytska, V.; Andrieux, F.; Faynot, O. & Raskin, J.-P. Substrate effects in sub-32 nm Ultra Thin SOI MOSFETs with Thin Buried Oxide

    [Abstract] [BibTeX]

    		2009 (Euro SOI 2009) - Conference Proceedings, pp. 27-28   inproceedings    
    Abstract: This paper underpins the influence of space-charge condition at the substrate / BOX interface, as a function of the gate length, on the front threshold voltage (VTHf) and subthreshold slope (S) of sub-32 nm Ultra Thin body (UTB) SOI MOSFETs with very thin buried oxide (UTB$^2$).
    BibTeX: 
    
@inproceedings{2009_EuroSOI_Conf_Burignat,
  author = {S. Burignat and D. Flandre and V. Kilchytska and F. Andrieux and O. Faynot and J.-P. Raskin},
  title = {Substrate effects in sub-32 nm Ultra Thin SOI MOSFETs with Thin Buried Oxide},
  booktitle = {Euro SOI 2009 - Conference Proceedings},
  year = {2009},
  pages = {27-28}
}
    Rudenko, T.; Kilchytska, V.; Burignat, S.; Raskin, J.-P.; Andrieu, F.; Faynot, O.; Nazarov, A.; Lysenko, V.-S. & Flandre, D. Transconductance and Mobility Behaviors in UTB SOI MOSFETs with Standard and Thin BOX

    [Abstract] [BibTeX]

    		2009 (Euro SOI 2009) - Conference Proceedings, pp. 111-112   inproceedings    
    Abstract: In this paper, we analyze the effects of the front and back interfaces on the transport properties in undoped ultra-thin body (UTB) SOI MOSFETs with standard and ultra-thin buried oxides (BOX), using measurements of the transconductance, gate-to-channel capacitance and carrier mobility at various back gate biases.
    BibTeX: 
    @inproceedings{2009_EuroSOI_Conf_Rudenko,
  author = {T. Rudenko and V. Kilchytska and S. Burignat and J.-P. Raskin and F. Andrieu and O. Faynot and A. Nazarov and V.-S. Lysenko and D. Flandre},
  title = {Transconductance and Mobility Behaviors in UTB SOI MOSFETs with Standard and Thin BOX},
  booktitle = {Euro SOI 2009 - Conference Proceedings},
  year = {2009},
  pages = {111-112}
}
    Kranti, A.; Burignat, S.; Raskin, J.-P. & Armstrong, G.A. Underlap channel UTBB MOSFETs for low-power analog/RF applications

    [Abstract] [BibTeX]

    		2009 Proc. 10th International Conference on Ultimate Integration of Silicon (ULIS 2009) , pp. 173-176   inproceedings DOI    
    Abstract: In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully-depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement > 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer-to-straggle ratio (s/sigma), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/sigma ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (< 60 muA/mum). The present work provides new viewpoints for realizing future low-power analog devices/circuits with underlap UTBB FETs.
    BibTeX: 
    @inproceedings{2009_ULIS_Kranti,
  author = {Kranti, A. and Burignat, S. and Raskin, J.-P. and Armstrong, G. A. },
  title = {Underlap channel UTBB MOSFETs for low-power analog/RF applications},
  booktitle = {Proc. 10th International Conference on Ultimate Integration of Silicon ULIS 2009},
  year = {2009},
  pages = {173--176},
  doi = {http://dx.doi.org/10.1109/ULIS.2009.4897564}
}
    O'Connor, I.; Liu, J.; Navarro, D.; Hassoune, I.; Burignat, S. & Gaffiot, F. Ultra-fine grain reconfigurability using CNTFETs

    [Abstract] [BibTeX]

    		2007 Proc. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007) , pp. 194-197   inproceedings DOI    
    Abstract: This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbon nanotube field-effect transistors (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Through simulations using available models, these gates and a 10-function ALU offering fine-grain reconfigurability are shown to operate at 20GHz.
    BibTeX: 
    @inproceedings{2007_IEEE_ICECS_OConnor,
  author = {O'Connor, I. and Liu, J. and Navarro, D. and Hassoune, I. and Burignat, S. and Gaffiot, F.},
  title = {Ultra-fine grain reconfigurability using CNTFETs},
  booktitle = {Proc. 14th IEEE International Conference on Electronics, Circuits and Systems ICECS 2007},
  year = {2007},
  pages = {194--197},
  doi = {http://dx.doi.org/10.1109/ICECS.2007.4510963}
}
    Burignat, S.; Plossu, C. & Boivin, P. Spatial and energetical profiles of defects extracted from ultra-low level trap-assisted leakage current in non-volatile floating thin tunnel oxide memory devices by using direct and floating gate technique measurements

    [Abstract] [BibTeX]

    		2007 Journal of Non-crystalline Solids
    Vol. 353 (16-17) , pp. 1624-1630       		article DOI    
    Abstract: Stress Induced Leakage Currents (SILC) remain one of the main reliability problem preventing further SiO2 tunnel oxide thickness reduction in FLOTOX EEPROM devices. In this work we present ultra-low level SILC current-voltage (I-V) measurements performed by using the floating gate technique on 7-8 nm thick SiO2 tunnel oxides and low-level measurements performed by direct technique measurements. Experimental characteristics performed by indirect measurement technique are reaching level as low as 2.10-17 A. They present new phenomena as negative differential resistance behavior and current threshold voltages. A physical one-step tunneling model (A-mode) taking into account the influence of defects located in the bulk SiO2 is proposed. Both spatial and energetical defect profiles are extracted from experimental data. We show that the new phenomena experimentally observed can be interpreted as a one step trap-assisted tunneling mechanism via defects located near the middle oxide even for highly stressed components.
    BibTeX: 
    
@article{2007_JNCS_Burignat,
  author = {S. Burignat and C. Plossu and P. Boivin},
  title = {Spatial and energetical profiles of defects extracted from ultra-low level trap-assisted leakage current in non-volatile floating thin tunnel oxide memory devices by using direct and floating gate technique measurements},
  journal = {Journal of Non-crystalline Solids},
  year = {2007},
  volume = {353},
  number = {16-17},
  pages = {1624-1630},
  note = {Jounal of Non-Crystalline Solids},
  doi = {http://dx.doi.org/10.1016/j.jnoncrysol.2007.01.021}
}
    Duguay, S.; Burignat, S.; Kern, P.; Grob, J.; Souifi, A. & Slaoui, A. Retention in Metal-Oxide-Semiconductor Structures with two embedded self-aligned Ge-nanocrystal layers

    [Abstract] [BibTeX]

    		2007 Semiconductor Science and Technology
    Vol.22 pp.837-842       		article DOI    
    Abstract: Structural and electrical characterization have been carried out on metal-oxide-semiconductor (MOS) structures with a silicon dioxide (SiO2) layer containing a germanium nanocrystals (Ge-ncs) floating gate. Ge-ncs layers were embedded in SiO2 by ion implantation with subsequent annealing. Structural analysis proved the presence of two self-aligned nanocrystal layers within the SiO2 host material. The electrical results indicate a strong memory effect due to the presence of a near-interface Ge-nc layer. Few volts memory windows can easily be obtained at relatively low programming voltages (< 6V). For comparison, operating voltages used in current FLASH technology are about 12 V. Despite its promising structural properties, retention times extracted from capacitance measurements and scanning Kelvin microscopy were found too low (~ 105 s) to comply with the non-volatility industry requirements (< 10 years required).
    BibTeX: 
    
@article{2007_SST_Dugay,
  author = {Duguay, S. and Burignat, S. and Kern, P. and Grob, J.J. and Souifi, A. and Slaoui, A.},
  title = {Retention in Metal-Oxide-Semiconductor Structures with two embedded self-aligned Ge-nanocrystal layers},
  journal = {Semiconductor Science and Technology},
  year = {2007},
  volume = {(Under Review)},
  doi = {http://dx.doi.org/10.1088/0268-1242/22/8/001}
}
    Duguay, S.; Slaoui, A.; Grob, J.; Kanoun, M.; Burignat, S. & Souifi, A. Structural properties of Ge-implanted SiO2 layers and related MOS memory effects

    [Abstract] [BibTeX]

    		2005 European Material Research Society (E-MRS) Spring Conference, Symposium on Materials Science and Device Issues for Future Si-based Technologies   inproceedings   URL 
    Abstract: Recently, the feasibility of using ion implantation of germanium and high temperature annealing to fabricate a near-interface nanocrystal (nc) layer into a silicon dioxide (SiO2) on Si film has been demonstrated. In this work, the influence of ion implantation parameters on the nc layer formation in SiO2 is studied. Transmission electron microscopy and Rutherford backscattering spectroscopy have been used to study the Ge-redistribution in the SiO2 films. Depending on the ion implantation energy and dose, the formation of a bulk nc layer in addition to the desired near-interface layer can be observed. A maximum near-interface Ge-nc density of 1.7 Ã— 1012 cm–2 has been measured. Capacitance-voltage measurements have been used to study electrical properties of metal-oxide-semiconductor structures containing such implanted SiO2 films. The results indicate a strong memory effect due to the presence of near-interface Ge-nc. As an example, flat-band shifts of 4.5 V have been obtained at a programming voltage of 7 V for 1 s. For the first time, long retention properties have been demonstrated on a memory structure containing a single near-interface Ge-nc layer.
    BibTeX: 
    @inproceedings{2005_EMRS_Duguay,
  author = {S. Duguay and A. Slaoui and J.J. Grob and M. Kanoun and S. Burignat and A. Souifi},
  title = {Structural properties of Ge-implanted SiO2 layers and related MOS memory effects},
  booktitle = {European Material Research Society (E-MRS) Spring Conference, Symposium on Materials Science and Device Issues for Future Si-based Technologies},
  year = {2005},
  url = {http://www.sciencedirect.com/science/article/B6TXF-4H9YC88-2/2/38e94600eee6b9ffefc89bfc39ae21ca}
}
    Burignat, S.; Baboux, N.; Plossu, C. & Boivin, P. EEPROM retention time extrapolation from floating gate SILC measurements

    [Abstract] [BibTeX]

    		2005 Proceedings of The 1st International Conference on Memory Technology and Design (ICMTD 2005) - FP5, pp.251-254   inproceedings  
    Abstract: This work presents new experimental data on ultra-low level Stress Induced Leakage Currents measured in 7 - 8 nm EEPROM tunnel oxides at room temperature, by using the the floating gate technique. Current-voltage characteristics are successfully modelized by to a one-step tunneling model taking into account the spatial and energetical profiles of defects in SiO2. New phenomena are pointed out, as negative differential resistance and the appearing of threshold voltages below which a rapid decrease of the conduction current is observed. According to our model, these behaviors can be well-simulated considering discrete defects energy levels in the SiO2 bandgap. Threshold voltages measured around 2 to 3 V appear to be very close to retention conditions floating gate potentials in EEPROM cells. According to a simple model, EEPROM retention times are extrapolated and it is shown that the particular behavior of SILC currents could explain the fact that retention times remain in the product specifications even for hardly cycled cells.
    BibTeX: 
    
@inproceedings{2005_ICMDT_Burignat,
  author = {Burignat, S. and Baboux, N. and Plossu, C. and and Boivin, P.},
  title = {EEPROM retention time extrapolation from floating gate SILC measurements},
  booktitle = {Proceedings of The 1st International Conference on Memory Technology and Design - FP5},
  year = {2005},
  series = {SESSION F : Memories and high- k dielectrics (FP5)},
  pages = {251--254},
  address = {Giens, France},
  month = {May 21- 24},

}
    Duguay, S.; Slaoui, A.; Grob, J.; Kanoun, M.; Burignat, S. & Souifi, A. Structural properties of Ge-implanted SiO2 layers and related MOS memory effects

    [Abstract] [BibTeX]

    		2005 Materials Science and Engineering: B
    Vol. 124-125 EMRS 2005, Symposium D - Materials Science and Device Issues for Future Technologies , pp. 488-493       		article DOI   URL 
    Abstract: Recently, the feasibility of using ion implantation of germanium and high temperature annealing to fabricate a near-interface nanocrystal (nc) layer into a silicon dioxide (SiO2) on Si film has been demonstrated. In this work, the influence of ion implantation parameters on the nc layer formation in SiO2 is studied. Transmission electron microscopy and Rutherford backscattering spectroscopy have been used to study the Ge-redistribution in the SiO2 films. Depending on the ion implantation energy and dose, the formation of a bulk nc layer in addition to the desired near-interface layer can be observed. A maximum near-interface Ge-nc density of 1.7 x 1012 cm-2 has been measured. Capacitance-voltage measurements have been used to study electrical properties of metal-oxide-semiconductor structures containing such implanted SiO2 films. The results indicate a strong memory effect due to the presence of near-interface Ge-nc. As an example, flat-band shifts of 4.5 V have been obtained at a programming voltage of 7 V for 1 s. For the first time, long retention properties have been demonstrated on a memory structure containing a single near-interface Ge-nc layer.
    BibTeX: 
    
@article{2005_MSE_B_Duguay,
  author = {Duguay, S. and Slaoui, A. and Grob, J.J. and Kanoun, M. and Burignat, S. and Souifi, A.},
  title = {Structural properties of Ge-implanted SiO2 layers and related MOS memory effects},
  booktitle = {EMRS 2005, Symposium D - Materials Science and Device Issues for Future Technologies},
  journal = {Materials Science and Engineering: B},
  year = {2005},
  volume = {124-125},
  pages = {488--493},
  url = {http://www.sciencedirect.com/science/article/B6TXF-4H9YC88-2/2/38e94600eee6b9ffefc89bfc39ae21ca},
  doi = {http://dx.doi.org/10.1016/j.mseb.2005.08.089}
}
    Croci, S.; Plossu, C. & Burignat, S. Capacitance and current-voltage simulation of EEPROM technology highly doped MOS structures

    [Abstract] [BibTeX]

    		2003 Journal of Materials Science: Materials in Electronics
    Vol. 14 , pp. 311-314       		article DOI   URL 
    Abstract: Abstract In this work, experimental capacitance (C-V) and current-voltage (I-V) data of electrically erasable programmable read-only memories (EEPROM) technology MOS structures were simulated. A specific test structure called a double-poly MOS capacitor reproducing the different stacked layers of an EEPROM cell state transistor has been used (7.2 nm SiO2 oxide, highly doped n+ substrate). Our aim was to research the most relevant model that allows a reliable extraction of electrical parameters and that could be easily introduced in industrial EEPROM devices simulators. To simulate C-V data, different classical and quantum models for the estimation of the semiconductor charge have been considered. Due to the substrate high-doping level and to the occurrence of Fowler-Nordheim (FN) injection, the available voltage domain for C-V recordings is reduced, which does not allow to distinguish between the different theoretical models predictions. I-V data were simulated using the classical FN model in which the oxide electric field-gate voltage relationship was extracted from the different C-V models mentioned above. Moreover, an iterative procedure we have proposed in a previous study has also been considered. It is shown that all the models lead to very comparable I-V simulations. These results let us conclude that the very time-consuming resolution of Schrödinger-Poisson coupled equations in a complete quantum approach is not necessary and that classical models remain sufficiently precise and reliable.
    BibTeX: 
    
@article{2003_JMS_ME_Croci,
  author = {Croci, S. and Plossu, C. and Burignat, S.},
  title = {Capacitance and current-voltage simulation of EEPROM technology highly doped MOS structures},
  journal = {Journal of Materials Science: Materials in Electronics},
  year = {2003},
  volume = {14},
  pages = {311-314},
  url = {http://www.springerlink.com/content/n5037677j3v33r81/},
  doi = {http://dx.doi.org/10.1023/A:1023919811012}
}
    Baboux, N.; Busseret, C.; Plossu, C.; Burignat, S.; Balland, B. & Boivin, P. Towards a model linking tunnel oxide degradation to programming window closure in EEPROM cells

    [Abstract] [BibTeX]

    		2003 Journal Of Non-Crystalline Solid
    Vol. 322 (1-3) , pp. 240-245       		article DOI   URL 
    Abstract: One of the main reliability problem in electrically erasable programmable read only memory (EEPROM) devices is the progressive closure of the programming window as the number of applied write/erase cycles is increased. This closure is qualitatively attributed to the build-up of fixed negative charge in the tunnel oxide during Fowler-Nordheim (FN) electron injection. Electron trapping induces FN current voltage shifts and consequently variations of the charge accumulated into the floating gate during one programming operation. In this work, we present an analytical quantitative model linking these shifts representative of oxide charging, to EEPROM cells threshold voltages in programmed states. This model is based on a simple electrical equivalent circuit and predicts a linear relationship between threshold and FN injection voltages shifts. The proportional constant is only dependent on the control gate-floating gate capacitive coupling ratio. Using a specific EEPROM-like test structure, the proposed model has been experimentally validated.
    BibTeX: 
    
@article{2003_JNCS_Baboux,
  author = {Baboux, N. and Busseret, C. and Plossu, C. and Burignat, S. and Balland, B. and Boivin, P.},
  title = {Towards a model linking tunnel oxide degradation to programming window closure in EEPROM cells},
  journal = {Journal Of Non-Crystalline Solid},
  year = {2003},
  volume = {322},
  number = {1-3},
  pages = {240-245},
  url = {http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TXM-48TKK6Y-C&_coverDate=07%2F15%2F2003&_alid=476012175&_rdoc=1&_fmt=&_orig=search&_qd=1&_cdi=5594&_sort=d&view=c&_acct=C000047341&_version=1&_urlVersion=0&_userid=884697&md5=5118016d7556069ccac6a2ea2073181d},
  doi = {http://dx.doi.org/10.1016/S0022-3093(03)00208-4}
}
    Busseret, C.; Baboux, N.; Plossu, C.; Burignat, S. & Boivin, P. Quantitative study of charge trapping in SiO2 during bipolar Fowler-Nordheim injection

    [Abstract] [BibTeX]

    		2003 Journal Of Non-Crystalline Solids
    Vol. 322 (1-3) , pp. 191-198       		article DOI   URL 
    Abstract: This work deals with the programming window closure observed in electrically erasable programmable read only memories as the number of write/erase cycles increases. This aging phenomenon is attributed to the build-up of oxide charge in the tunnel area. Capacitance-voltage and current-voltage measurements on 8.5 nm thick oxide MOS capacitors performed after constant current Fowler-Nordheim (FN) stresses showed interface states generation at both the anode and the cathode. A linear build-up of 'slow' states with the total injected charge was also observed at the cathode. Bulk oxide trapped charge and normalized centroid were deduced from the DiMaria technique. The bulk oxide charge build-up after FN stress is shown to follow a power law as a function of injected electron density over several decades. The charging kinetics have been explained by two components: trapping by native and generated traps. We have determined the different trap parameters (densities, capture cross-sections, generation rates and locations). By varying the stress current (polarity and density), we have noticed that the change in generated trap parameters is linear with the stress bias. We take finally a particular interest in the cumulating effects of different stresses. To our knowledge, such a complete study is absent from the literature and has to be done to predict the charge trapping kinetics due to non-constant stress which occur during memory write and erase operations.
    BibTeX: 
    
@article{2003_JNCS_Busseret,
  author = {Busseret, C. and Baboux, N. and Plossu, C. and Burignat, S. and Boivin, P.},
  title = {Quantitative study of charge trapping in SiO2 during bipolar Fowler-Nordheim injection},
  journal = {Journal Of Non-Crystalline Solids},
  year = {2003},
  volume = {322},
  number = {1-3},
  pages = {191-198},
  url = {http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TXM-48TKK6Y-5&_coverDate=07%2F15%2F2003&_alid=476012304&_rdoc=1&_fmt=&_orig=search&_qd=1&_cdi=5594&_sort=d&view=c&_acct=C000047341&_version=1&_urlVersion=0&_userid=884697&md5=58d1445b84bc3b70db7592f5012aa56f},
  doi = {http://dx.doi.org/10.1016/S0022-3093(03)00201-1}
}
    Burignat, S.; Croci, S.; Plossu, C. & Boivin, P. Extraction of MOS Capacitance in Fowler-Nordheim Regime Using the Floating Gate Technique

    [Abstract] [BibTeX]

    		2002 Proceedings of the 4th Internationnal Conference on Material for Microelectronics and Engineering (MFMN 2002)   inproceedings    
    Abstract: The floating gate technique (FGT) is a very sensitive method to measure very low level leakage currents in MOS capacitors. This indirect technique requires the precise knowledge of the capacitance of the structure under test. We have studied the impact of the capacitance model (classic or quantum) and of polysilicon gate depletion effect. We have shown that for 7.2 nm thin EEPROM tunnel oxides, a classical capacitance-voltage model remains valid. In a second part, we present a new method to extract the apparent MOS capacitance in the Fowler- Nordheim (FN) injection range of potentials which cannot be obtained by direct quasi-static capacitance measurements. By reference to direct current-voltage measurements, capacitance values at high electric fields are extracted from FGT current measurements.
    BibTeX: 
    @inproceedings{2002_MFMN_Burignat,
  author = {Burignat, S. and Croci, S. and Plossu, C. and Boivin, P.},
  title = {Extraction of MOS Capacitance in Fowler-Nordheim Regime Using the Floating Gate Technique},
  booktitle = {Proceedings of the 4th Internationnal Conference on Material for Microelectronics and Engineering (MFMN)},
  year = {2002}
}
    Croci, S.; Plossu, C.; Burignat, S. & Boivin, P. Capacitance and Current-Voltage Simulation of EEPROM Technology Highly Doped MOS Structure

    [Abstract] [BibTeX]

    		2002 Proceedings of the 4th Internationnal Conference on Material for Microelectronics and Engineering (MFMN) , pp. 311-314   inproceedings
    Abstract: Abstract In this work, experimental capacitance (C-V) and current-voltage (I-V) data of electrically erasable programmable read-only memories (EEPROM) technology MOS structures were simulated. A specific test structure called a double-poly MOS capacitor reproducing the different stacked layers of an EEPROM cell state transistor has been used (7.2 nm SiO2 oxide, highly doped n+ substrate). Our aim was to research the most relevant model that allows a reliable extraction of electrical parameters and that could be easily introduced in industrial EEPROM devices simulators. To simulate C-V data, different classical and quantum models for the estimation of the semiconductor charge have been considered. Due to the substrate high-doping level and to the occurrence of Fowler-Nordheim (FN) injection, the available voltage domain for C-V recordings is reduced, which does not allow to distinguish between the different theoretical models predictions. I-V data were simulated using the classical FN model in which the oxide electric field-gate voltage relationship was extracted from the different C-V models mentioned above. Moreover, an iterative procedure we have proposed in a previous study has also been considered. It is shown that all the models lead to very comparable I-V simulations. These results let us conclude that the very time-consuming resolution of Schrödinger-Poisson coupled equations in a complete quantum approach is not necessary and that classical models remain sufficiently precise and reliable.
    BibTeX: 
    @inproceedings{2002_MFMN_Croci,
  author = {Croci, S. and Plossu, C. and Burignat, S. and Boivin, P.},
  title = {Capacitance and Current-Voltage Simulation of EEPROM Technology Highly Doped MOS Structure},
  booktitle = {Proceedings of the 4th Internationnal Conference on Material for Microelectronics and Engineering (MFMN)},
  year = {2002},
  pages = {311-314},
  url = {http://www.springerlink.com/content/n5037677j3v33r81/},
  doi = {http://dx.doi.org/10.1023/A:1023919811012}
}
    Busseret, C.; Baboux, N.; Plossu, C.; Burignat, S. & Boivin, P. Quantitative Study of Charge Trapping in SiO2 During Bipolar Fowler-Nordheim Injection

    [Abstract] [BibTeX]

    		2002 Proceedings of the 4th Franco-Italian Symposium on SiO2 and Advanced Dielectrics (SiO2 Conference 2002)   inproceedings
    Abstract: This work deals with the programming window closure observed in electrically erasable programmable read only memories as the number of write/erase cycles increases. This aging phenomenon is attributed to the build-up of oxide charge in the tunnel area. Capacitance-voltage and current-voltage measurements on 8.5 nm thick oxide MOS capacitors performed after constant current Fowler-Nordheim (FN) stresses showed interface states generation at both the anode and the cathode. A linear build-up of 'slow' states with the total injected charge was also observed at the cathode. Bulk oxide trapped charge and normalized centroid were deduced from the DiMaria technique. The bulk oxide charge build-up after FN stress is shown to follow a power law as a function of injected electron density over several decades. The charging kinetics have been explained by two components: trapping by native and generated traps. We have determined the different trap parameters (densities, capture cross-sections, generation rates and locations). By varying the stress current (polarity and density), we have noticed that the change in generated trap parameters is linear with the stress bias. We take finally a particular interest in the cumulating effects of different stresses. To our knowledge, such a complete study is absent from the literature and has to be done to predict the charge trapping kinetics due to non-constant stress which occur during memory write and erase operations.
    BibTeX: 
    @inproceedings{2002_SiO2_Busseret,
  author = {Busseret, C. and Baboux, N. and Plossu, C. and Burignat, S. and Boivin, P.},
  title = {Quantitative Study of Charge Trapping in SiO2 During Bipolar Fowler-Nordheim Injection},
  booktitle = {Proceedings of the 4th Franco-Italian Symposium on SiO2 and Advanced Dielectrics},
  year = {2002},
  url = {http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TXM-48TKK6Y-5&_coverDate=07%2F15%2F2003&_alid=476012304&_rdoc=1&_fmt=&_orig=search&_qd=1&_cdi=5594&_sort=d&view=c&_acct=C000047341&_version=1&_urlVersion=0&_userid=884697&md5=58d1445b84bc3b70db7592f5012aa56f},
  doi = {http://dx.doi.org/10.1016/S0022-3093(03)00201-1}
}
    Baboux, N.; Busseret, C.; Plossu, C.; Burignat, S.; Balland, B. & Boivin, P. Towards a Model Linking Tunnel Oxide Degradation to Programming Window Closure in FLOTOX EEPROM Cells

    [Abstract] [BibTeX]

    		2002 Proceedings of the 4th Franco-Italian Symposium on SiO2 and Advanced Dielectrics (SiO2 Conference 2002)   inproceedings
    Abstract: One of the main reliability problem in electrically erasable programmable read only memory (EEPROM) devices is the progressive closure of the programming window as the number of applied write/erase cycles is increased. This closure is qualitatively attributed to the build-up of fixed negative charge in the tunnel oxide during Fowler-Nordheim (FN) electron injection. Electron trapping induces FN current voltage shifts and consequently variations of the charge accumulated into the floating gate during one programming operation. In this work, we present an analytical quantitative model linking these shifts representative of oxide charging, to EEPROM cells threshold voltages in programmed states. This model is based on a simple electrical equivalent circuit and predicts a linear relationship between threshold and FN injection voltages shifts. The proportional constant is only dependent on the control gate-floating gate capacitive coupling ratio. Using a specific EEPROM-like test structure, the proposed model has been experimentally validated.
    BibTeX: 
    
@inproceedings{2002_SiO2_Conf_Baboux,
  author = {Baboux, N. and Busseret, C. and Plossu, C. and Burignat, S. and Balland, B. and Boivin, P.},
  title = {Towards a Model Linking Tunnel Oxide Degradation to Programming Window Closure in FLOTOX EEPROM Cells},
  booktitle = {Proceedings of the 4th Franco-Italian Symposium on SiO2 and Advanced Dielectrics},
  year = {2002},
  url = {http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TXM-48TKK6Y-C&_coverDate=07%2F15%2F2003&_alid=476012175&_rdoc=1&_fmt=&_orig=search&_qd=1&_cdi=5594&_sort=d&view=c&_acct=C000047341&_version=1&_urlVersion=0&_userid=884697&md5=5118016d7556069ccac6a2ea2073181d},
  doi = {http://dx.doi.org/10.1016/S0022-3093(03)00208-4}
}

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