Stéphane BURIGNAT

Revues Internationales :

S. Burignat, D. Flandre, M.K. Md Arshad, V. Kilchytska, F. Andrieu, O. Faynot and J.-P. Raskin Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel, Solid-State Electronics 54, (2010) pp.213-219.

T. Rudenko, V. Kilchytska, S. Burignat, J.-P. Raskin, F. Andrieu, O. Faynot, Y.L. Tiec, K. Landry, A. Nazarov, V. Lysenko, and D. Flandre Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides, Solid-State Electronics 54, (2010) pp.164-170.

S. Duguay, S. Burignat, P. Kern, J.J. Grob, A. Slaoui , A. Souifi, Retention in Metal-Oxide-Semiconductor Structures with two embedded self-aligned Ge-nanocrystal layers, Semiconductor Science and Technology 22 (2007), pp.837-842.

S.Burignat, C. Plossu, and P.Boivin, Spatial and energetical profiles of defects extracted from ultra-low level SILC of EEPROM tunnel oxides by using direct and floating gate technique measurements, Journal Of Non-Crystalline Solids, 353(16-17) (2007), pp.1624-1630.

Conférences Internationales :

A. De Vos, S. Burignat & M. Thomsen, Reversible implementation of a disrete linear transformation, Reversible Computation, 2nd Workshop, Proceedings (RC 2010), July 2nd-3rd, 2010, Bremen, Germany (2010) (to be published in Journal of Multiple-Valued Logic and Soft Computing)

A. Kranti, R. Rashmi, S. Burignat; J-P. Raskin, & G. Armstrong Analog/RF Performance of sub-100nm SOI MOSFETs with Non-Classical Gate-Source/Drain Underlap Channel Design, 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems SiRF 2010, 11-13 January 2010, New Orleans, LA (2010)

S. Burignat, MK. Md Arshad, D. Flandre, V. Kilchytska, F. Andrieux, O.Faynot P. Scheiblin and J.-P. Raskin Drain / Substrate Coupling Impact on DIBL of Ultra Thin Body and Box SOI MOSFETs with undoped Channel, ESSDERC 2009 Conference, September 14-19, Athènes, Grèce (2009) pp.141-144. In session: Thin film 22nm CMOS and beyond.

A. Kranti, S. Burignat, J.-P. Raskin and G.A. Armstrong Underlap Channel UTBB MOS-FETs for Low-Power Analog/RF Applications,, Ultimate Integration on Silicon Conference - ULIS 2009 Conference, March 18-20, Aachen, Germany (2009).

S. Burignat, D. Flandre, V. Kilchytska, F. Andrieux, O.Faynot and J.-P. Raskin Substrate effects in sub-32 nm Ultra Thin SOI MOSFETs with Thin Buried Oxide, EuroSOI 2009 Conference, January 19-21, Göteborg, Sweden (2009). Selectionné pour publication dans Solid-State Electronics.

I. O'Connor, J. Liu, D. Navarro, I. Hassoune, S. Burignat, F. Gaffiot, Ultra-fine grain reconfigurability using CNTFETs, 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), December 11-14, Marrakech, Morocco (2007).

S.Burignat, S. Croci, C.Plossu, and P. Boivin, Extraction of MOS Capacitance in Fowler-Nordheim Regime Using the Floating Gate Technique, Materials for Microelectronics and Nanoengineering 10 - 12 June (2002), Hanasaari Cultural Centre, Espoo, Finland, (2002).

Ph.D Thesis (French) :

S.Burignat Mécanismes de Transport, Courants de Fuite Ultra-Faibles et Rétention dans les Mémoires non Volatiles à Grille Flottante , Thèse de Doctorat, INSA de Lyon, 10 Décembre 2004, Lyon.

S. Burignat, Conduction par pièges dans les films minces de dioxyde de silicium Étapes de développement d’un modèle de conduction assisté par pièges, Techniques de caractérisation associées et Étude des courants de fuites, Éditions Universitaires Européennes, ISBN-13: 978-6131513800 (2010), French, 268 pages